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AT86RF232
synthesizer is enabled. When the PLL has been settled at the receive frequency to a
channel defined by register bits CHANNEL (register 0x08, PHY_CC_CCA), refer to
Section 9.7.2 , a successful PLL lock
is indicated by issuing an interrupt
IRQ_0 (PLL_LOCK).
If an RX_ON command is issued in PLL_ON state, the receiver is enabled immediately.
If the PLL has not been settled before the state change nevertheless takes place. Even
if the register bits TRX_STATUS (register 0x01, TRX_STATUS) indicates RX_ON,
actual frame reception can only start once the PLL has locked.
The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4.
7.1.2.5 RX_ON and BUSY_RX – RX Listen and Receive State
In RX_ON state the receiver module and the PLL frequency synthesizer are enabled.
The Atmel AT86RF232 receive mode is internally separated into RX_ON state and
BUSY_RX state. There is no difference between these states with respect to the analog
radio transceiver circuitry, which is always turned on. In both states, the receiver and
the PLL frequency synthesizer are enabled.
During RX_ON state, the receiver listens for incoming frames. After detecting a valid
synchronization header (SHR), the AT86RF232 automatically enters the BUSY_RX
state. The reception of a valid PHY header (PHR) generates an IRQ_2 (RX_START)
and starts the PSDU data demodulation.
During PSDU reception, the frame data are stored continuously in the Frame Buffer
until the last byte was received. The completion of the frame reception is indicated by
an interrupt IRQ_3 (TRX_END) and the radio transceiver reenters the state RX_ON. At
the same time the register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated
with the result of the FCS check (see Section 8.2 ).
Received frames are passed to the frame filtering unit, refer to Section 7.2.3.4 . If the
content of the MAC addressing fields (refer to [1] IEEE 802.15.4-2006 Section 7.2.1) of
a frame matches to the expected addresses, which is further dependent on the
addressing mode, an address match interrupt IRQ_5 (AMI) is issued, refer to
Section 6.6 . The expected address values are to be stored in registers 0x20 – 0x2B
(Short address, PAN-ID and IEEE address). Frame filtering is available in Basic
Operating Mode and Extended Operating Mode, refer to Section 7.2.3.4 .
Leaving state RX_ON is possible by writing a state change command to register bits
TRX_CMD in register 0x02 (TRX_STATE).
7.1.2.6 BUSY_TX – Transmit State
A transmission can be initiated in state PLL_ON. There are two ways to start a
transmission:
? Rising edge of pin 11 (SLP_TR)
? TX_START command to register bits TRX_CMD (register 0x02, TRX_STATE).
Either of these takes the radio transceiver into the BUSY_TX state.
During the transition to BUSY_TX state, the PLL frequency shifts to the transmit
frequency. The actual transmission of the first data chip of the SHR starts after 16μs to
allow PLL settling and PA ramp-up, see Figure 7-6 . After transmission of the SHR, the
Frame Buffer content is transmitted. In case the PHR indicates a frame length of zero,
the transmission is aborted.
33
8321A – MCU Wireless – 10/11
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